Field effect transistors (FETs) are semiconductor devices that can be fabricated on a bulk semiconductor substrate or on a silicon-on-insulator (SOI) substrate. FET devices generally consist of a source terminal, a drain terminal, a gate terminal, and a channel between the source and drain. The gate terminal is separated from the channel by a thin insulating layer, typically of silicon oxide, called the gate oxide or gate dielectric. An applied potential at the gate modulates the conductivity of the channel between the source and drain thereby controlling the current flow between the source and the drain.
Structural elements of FET devices create parasitic capacitance that can limit the speed of high-frequency applications. Capacitance is the ability to store an electric charge, and parasitic capacitance is common inside electronic devices whenever two conductors are parallel to each other. Capacitance decreases with increased distance between two parallel conductors, usually separated by an insulator or dielectric material. Capacitance also decreases with decreased surface area of the parallel conductors involved, or with a decrease in the dielectric constant of the material between the conductors. Proper device design is, therefore, important to minimize the overall parasitic capacitance of FETs.